module dec68b title 'address decoder for 68k computer' dec68b device 'P22V10'; clk pin 1; as pin 2; a23 pin 3; a22 pin 4; a21 pin 5; a20 pin 6; vma pin 7; dtack pin 23 istype 'com'; ws3 pin 19 istype 'reg'; ws2 pin 22 istype 'reg'; ws1 pin 21 istype 'reg'; ws0 pin 20 istype 'reg'; vpa pin 18 istype 'com'; dev68vma pin 17 istype 'com'; "Memory Map " 0x000000-0x0fffff 1ws ROM " 0x100000-0x100000 0ws RAM " 0x200000-0xbfffff 14ws unused " 0xd00000-0xdfffff 4ws Intel style bus cycle - (using !rd, !wr) " 0xd00000-0xd0ffff 4ws fdc " 0xd10000-0xd1ffff 4ws unused " 0xd20000-0xd2ffff 4ws unused " 0xd30000-0xd3ffff 4ws unused " 0xd40000-0xd4ffff 4ws unused " 0xd50000-0xdfffff 4ws unused " 0xd60000-0xd6ffff 4ws unused " 0xd70000-0xd7ffff 4ws unused " 0xe00000-0xefffff - 68k peripheral - dtack generated by device " 0xe00000-0xe3ffff - 68681 " 0xe40000-0xe7ffff - unused " 0xe80000-0xebffff - unused " 0xec0000-0xefffff - unused " 0xf00000-0xffffff - 6800 peripheral - E type bus cycle " 0xf00000-0xf3ffff - unused " 0xf40000-0xf7ffff - unused " 0xf80000-0xfbffff - unused " 0xfc0000-0xffffff - unused ws = [ ws3, ws2, ws1, ws0 ]; " wait state counter addr = [ a23, a22, a21, a20 ]; rom_addr = ^h0; " ROM address ram_addr = ^h1; " RAM address devint_addr = ^hd; " Intel style peripheral address dev_addr = ^he; " 68k peripheral address dev68_addr = ^hf; " 6800 peripheral address H,L,X,C,Z = 1,0,.X.,.C.,.Z.; equations " simulate open-collector with a tri-state output " dtack raised by pullup resistor " as is deasserted at the end of S6, " ws will leave state 15 at the end of S7 " dtack will go high impedance at the end of as " passive pullup resistor will raise dtack " dtack must not be asserted for an interrupt acknowledge " !dtack = 1; " dtack.oe = !as & (ws == 15); " dtack raised by active high pulse " as is deasserted at the end of S6, " ws will leave state 15 at the end of S7 " dtack will be active pulled high during the S7 " and will go high impedance at the end of S7 " dtack must not be asserted for an interrupt acknowledge !dtack = !as; " pulse dtack high dtack.oe = (ws == 15); "low impedance while in state 15 !vpa = 1; vpa.oe = !as & (addr == dev68_addr); " decoded 6800 peripheral select with processor vma signal " use this for second level decoder enable !dev68vma = !as & (addr == dev68_addr) & !vma; dev68vma.oe = 1; ws.clk = clk; ws.oe = [ 1, 1, 1, 1 ]; " wait state generator " ram -> 0 wait states " rom -> 1 wait state " devint -> 4 wait states -- Intel style peripherals " dev68 -> 6800 type peripheral -- vpa, vma instead of dtack " everything else -> 14 wait states " 14 wait states acts as to force a bus cycle termination to " prevent a lockup of the processor. " 68000 peripherals must force dtack before the 14 cycle or " it will be done for them. " Important: !dtack must be asserted or processor will stall " State 14 is a hold state for a 6800 type peripheral state_diagram ws; state 0: if as then 0; else if (addr == ram_addr) then 15; else if (addr == dev68_addr) then 14; else goto 1; state 1: if as then 0; else if (addr == rom_addr) then 15; else goto 2; state 2: if as then 0; else goto 3; state 3: if as then 0; else goto 4; state 4: " 4 wait states if as then 0; else if (addr == devint_addr) then 15; else goto 5; state 5: if as then 0; else goto 6; state 6: if as then 0; else goto 7; state 7: if as then 0; else goto 8; state 8: if as then 0; else goto 9; state 9: if as then 0; else goto 10; state 10: if as then 0; else goto 11; state 11: if as then 0; else goto 12; state 12: if as then 0; else goto 13; state 13: if as then 0; else goto 15; state 14: if as then 0; else goto 14; " 6800 type peripheral, no !dtack allowed state 15: if as then 0; else goto 15; " dtack asserted, stay until as test_vectors ( [ as, addr, vma ]->[ vpa.oe, dev68vma ] ) [ 1, X, X ]->[ 0, 1 ]; [ 0, ^h0, X ]->[ 0, 1 ]; [ 0, ^h1, X ]->[ 0, 1 ]; [ 0, ^h2, X ]->[ 0, 1 ]; [ 0, ^h3, X ]->[ 0, 1 ]; [ 0, ^h4, X ]->[ 0, 1 ]; [ 0, ^h5, X ]->[ 0, 1 ]; [ 0, ^h6, X ]->[ 0, 1 ]; [ 0, ^h7, X ]->[ 0, 1 ]; [ 0, ^h8, X ]->[ 0, 1 ]; [ 0, ^h9, X ]->[ 0, 1 ]; [ 0, ^ha, X ]->[ 0, 1 ]; [ 0, ^hb, X ]->[ 0, 1 ]; [ 0, ^hc, X ]->[ 0, 1 ]; [ 0, ^hd, X ]->[ 0, 1 ]; [ 0, ^he, X ]->[ 0, 1 ]; [ 0, ^hf, 1 ]->[ 1, 1 ]; [ 0, ^hf, 0 ]->[ 1, 0 ]; test_vectors ( [ clk, as, addr, ws ]->[ ws ] ) [ C, 1, X, X ]->[ 0 ]; [ C, 0, 0, 0 ]->[ 1 ]; [ C, 0, 0, 1 ]->[ 15 ]; [ C, 0, 0, 15 ]->[ 15 ]; [ C, 1, 0, 15 ]->[ 0 ]; [ C, 0, 1, 0 ]->[ 15 ]; [ C, 0, 1, 15 ]->[ 15 ]; [ C, 1, 1, 15 ]->[ 0 ]; [ C, 0, 2, 0 ]->[ 1 ]; [ C, 0, 2, 1 ]->[ 2 ]; [ C, 0, 2, 2 ]->[ 3 ]; [ C, 0, 2, 3 ]->[ 4 ]; [ C, 0, 2, 4 ]->[ 5 ]; [ C, 0, 2, 5 ]->[ 6 ]; [ C, 0, 2, 6 ]->[ 7 ]; [ C, 0, 2, 7 ]->[ 8 ]; [ C, 0, 2, 8 ]->[ 9 ]; [ C, 0, 2, 9 ]->[ 10 ]; [ C, 0, 2, 10 ]->[ 11 ]; [ C, 0, 2, 11 ]->[ 12 ]; [ C, 0, 2, 12 ]->[ 13 ]; [ C, 0, 2, 13 ]->[ 15 ]; [ C, 0, 2, 15 ]->[ 15 ]; [ C, 1, 2, 15 ]->[ 0 ]; [ C, 0, ^he, 0 ]->[ 1 ]; [ C, 0, ^he, 1 ]->[ 2 ]; [ C, 0, ^he, 2 ]->[ 3 ]; [ C, 0, ^he, 3 ]->[ 4 ]; [ C, 0, ^he, 4 ]->[ 5 ]; [ C, 0, ^he, 5 ]->[ 6 ]; [ C, 0, ^he, 6 ]->[ 7 ]; [ C, 0, ^he, 7 ]->[ 8 ]; [ C, 0, ^he, 8 ]->[ 9 ]; [ C, 0, ^he, 9 ]->[ 10 ]; [ C, 0, ^he, 10 ]->[ 11 ]; [ C, 0, ^he, 11 ]->[ 12 ]; [ C, 0, ^he, 12 ]->[ 13 ]; [ C, 0, ^he, 13 ]->[ 15 ]; [ C, 0, ^he, 15 ]->[ 15 ]; [ C, 1, ^he, 15 ]->[ 0 ]; [ C, 0, ^hf, 0 ]->[ 14 ]; [ C, 0, ^hf, 14 ]->[ 14 ]; [ C, 1, ^hf, 14 ]->[ 0 ]; [ C, 0, ^hd, 0 ]->[ 1 ]; [ C, 0, ^hd, 1 ]->[ 2 ]; [ C, 0, ^hd, 2 ]->[ 3 ]; [ C, 0, ^hd, 3 ]->[ 4 ]; [ C, 0, ^hd, 4 ]->[ 15 ]; [ C, 0, ^hd, 15 ]->[ 15 ]; [ C, 1, ^hd, 15 ]->[ 0 ]; end dec68b